1. Field of the Invention
The field of the invention is that of circuits for generating clock signals, and it relates more particularly to a circuit designed to recover a clock rate from a reference clock in which there are missing transitions. The circuit of the invention is required, in particular, to be suitable for recovering clocks at different frequencies, i.e. it must present the ability to operate at multiple rates.
2. Description of the Related Art
Below in this description, the context is one of a transmission system, e.g. a microwave system, in which digital data is transmitted in quasi-synchronous frames. Each frame conveys a plurality of calls, and a receiver of the frames demultiplexes the received data in order to apply it to different paths, each corresponding to a different destination. Each path has a clock frequency corresponding thereto.
For the purpose of being written into a buffer memory, the data on each path, and the outlet from the demultiplexing system, are synchronized by means of a clock having "holes", i.e. in which some transitions are missing. These holes come from justification during multiplexing on transmission, from the absence of other paths, and from information bits being inserted into the frame (frame clock word, parity bits, error correcting code, etc.). In order to enable the received data to be read back properly, it is necessary to regenerate a clock that does not have any holes, i.e. in which the transitions are regular. For this purpose, it is common practice to use a phase-locked loop that is designed to deliver a regular clock, having the same frequency as the mean frequency of the clock having holes, and for use in reading the data that is stored temporarily in the buffer memory.
Three different transmission rates (1.544 Mbit/s, 2.048 Mbit/s, and 8.448 Mbit/s) are taken into consideration below, thus requiring three different clock frequencies to be recovered. The accuracies of the clocks to be recovered in the systems under consideration are: .+-.50 ppm for data rates of 1.544 Mbit/s and 2.048 Mbit/s, and of .+-.30 ppm for the data rate of 8.448 Mbit/s.
The invention proposes a solution that is digital rather than analog for performing the clock recovery function for reasons of modularity, of reusability (reprogrammable components), of integration, and of cost (suitable for implanting in application specific integrated circuits (ASICs)).
The present invention seeks in particular to satisfy the following CCITT recommendations: G823 (or G824 for US data rates) concerning maximum acceptable jitter at a hierarchical interface; G921 concerning residual jitter; G703 concerning clock accuracy and pulse specifications; G751 for multiplexing and/or demultiplexing at framed rates of 34.368 Mbit/s (i.e. 4*8.448 Mbit/s) with positive justification for jitter transfer; G742 for multiplexing and/or demultiplexing at the rate of 2.048 Mbit/s with positive justification for jitter transfer; and G743 for multiplexing and/or demultiplexing a tributary rate of 1.544 Mbit/s for jitter transfer.
European patent application No. 0 471 506 discloses a digital circuit suitable for regenerating a regular clock signal from a clock having holes. Nevertheless, that circuit operates only if the clock to be recovered is a clock that is synchronous with the transmitted signal and it assumes that the clock to be recovered is a rational function of the clock with holes. That circuit is therefore unsuitable for use with a quasi-synchronous transmission system where each of the various tributaries has its own clock.